Digital channelizer having efficient architecture for cyclic...

Details Digital channelizer having efficient architecture for cyclic... Digital channelizer having efficient architecture for cyclic...

H - Electricity

04

J

H04J 1/08 (2006.01) H04J 1/05 (2006.01) H04L 5/06 (2006.01)

Patent

CA 2298999

The invention is a digital channelizer and a process for dividing an input bandwidth into at least some of N channels. A digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes a window presum (102); a cyclic shift (24'), coupled to the I output groups of date words, having I cyclic shift paths, each cyclic shift path being responsive to a different output group of data words to produce I output groups of data words, each cyclic shift path comprising a plurality of word shifting elements each responsive to a group of data words; and a discrete Fourier transform (26') coupled to the I output groups of cyclically shifted data words outputted from the cyclic shift.

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