Digital channelizer having efficient architecture for presum...

Details Digital channelizer having efficient architecture for presum... Digital channelizer having efficient architecture for presum...

H - Electricity

04

L

H04L 25/14 (2006.01) G06F 17/14 (2006.01) H03H 17/02 (2006.01)

Patent

CA 2298872

The invention is a digital channelizer and a process for dividing an input bandwidth into at least some of N channels. A digital channelizer which divides an input bandwidth into channels in accordance with the invention includes a window presum (102), responsive to input data, which outputs real or complex data; a cyclic shift (24'), coupled to the real or complex data outputted from the window presum, which outputs real or complex data which is shirred relative to data outputted from the window presum; and an N point discrete Fourier transform apparatus (26'), coupled to the shifted real or complex data, which in response to a command performs a discrete Fourier transform on inputted shifted real or inputted shifted complex data to produce the channels, the discrete Fourier transform apparatus performing a transformation of the inputted cyclic shifted real data when the command specifies processing of the shifted real data and performing a transformation of the inputted complex data when the command specifies processing of the inputted cyclic shifted complex data. The N point discrete Fourier transform includes an input discrete Fourier computation stage having two N/2 point discrete Fourier transforms and an output discrete Fourier computation stage having N/2 two point discrete Fourier transforms.

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