Digital class receiver

Details Digital class receiver Digital class receiver

H - Electricity

04

B

H04B 1/16 (2006.01) H04B 1/06 (2006.01) H04L 27/14 (2006.01)

Patent

CA 2069142

A class message receiver that in one embodiment can be implemented in a Digital Signal Processor. An FSK demodulator takes input linear samples of the signal and filters them with a bandpass filter which does an upsampling to increase the sampling rate from 8,000 Hz to 24,000 Hz, which results in 20 samples at the output of the bandpass filter for each incoming data bit. The amplitude of the signal/samples at the output of the bandpass filter is adjusted by an automatic gain control (AGC) circuit and the resulting samples (for convenience referred as sample (t), where t is a discrete moment in time) are processed along two different paths designed to estimate the likelihood of the input signal encoding a mark (mark estimation path) or a space (space estimation path).

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