Digital clock buffer circuit providing controllable delay

Details Digital clock buffer circuit providing controllable delay Digital clock buffer circuit providing controllable delay

H - Electricity

03

K

328/87

H03K 5/135 (2006.01) G06F 1/10 (2006.01) H03L 7/081 (2006.01) H03L 7/087 (2006.01) H03L 7/089 (2006.01)

Patent

CA 2037593

-38- Abstract of the Disclosure A clock buffer circuit that generates a local clock signal in response to a sys-tem clock signal. The clock buffer circuit includes a buffer circuit for generating the local clock signal in response to an intermediate clock signal. A buffer control cir- cuit generates the intermediate clock signal in response to the system clock signal and the local clock signal. The buffer control circuit provides a variable delay so that, with an additional delay provided by the buffer circuit, the local clock signal has a selected phase relationship in relation to the system clock signal.

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