Digital clock dejitter circuits for regenerating clock...

Details Digital clock dejitter circuits for regenerating clock... Digital clock dejitter circuits for regenerating clock...

H - Electricity

04

L

H04L 7/00 (2006.01) H04J 3/07 (2006.01)

Patent

CA 2125289

A digital clock dejitter circuit includes a RAM (20) for receiv- ing an incoming gapped signal (14a), a digital, fractional RAM full- ness gauge (30) for tracking the average input and output rates to and from the RAM and for generating therefrom a control indica- tion, and a controllable digital frequency generator (40) for receiving a fast clock signal and the control indication, and for providing therefrom a substantially jitter-free clock signal at the same nominal rate as the incoming gapped signal. The RAM fullness gauge (30) comprises write (54) and read (56) counters which track the move- ment of data into and out of the RAM, and a subtractor (58) for tak- ing the difference of the counters to obtain the integer value of the RAM depth. The controllable digital frequency generator (40) com- prises an adder (72), a register (74) and a fast clock divider (FCC) (76) which provides the fullness gauge with a fractional digital indi- cation of the RAM depth.

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