Digital conference circuit

Details Digital conference circuit Digital conference circuit

H - Electricity

04

M

344/14

H04M 3/56 (2006.01)

Patent

CA 1246725

ABSTRACT OF THE DISCLOSURE The disclosed digital conference circuit additively combines conference signals with a single adder, a partial sum, accumulator RAM, and conversion ROMS. Internal conferencing time slots are dynamically assignable via a microprocessor controlled channel indexing memory. The signal level on lines can be selectively adjusted to compensate for loop attenuation or a per-line basis. The circuit can operate with a number of voice coding law PCM signals from CODECs by the use of conversion ROMs containing conversion tables for the selected voice coding law. Additive background noise levels may be reduced by the dynamic selection of modified sections of the conversion tables. The number of conferences available and the number of lines per conference is limited only by the number N of internal conferencing PCM time slots. The number of internal conferencing time slots used per conference equals the square of the number of lines in the conference. The total number of multi-line conferences possible at any one time is determined by determining the number of internal conferencing time slots required per multi-line conference and fitting this into the N PCM time slot total available space. Conference capacity can be increased by increasing the number of internal conferencing time slots per frame.

488531

Affiliated with

Also associated with

Rating

Digital conference circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital conference circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital conference circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1233874