Digital data processor with fault tolerant peripheral bus...

Details Digital data processor with fault tolerant peripheral bus... Digital data processor with fault tolerant peripheral bus...

G - Physics

06

F

354/231

G06F 11/00 (2006.01) G06F 11/07 (2006.01) G06F 11/16 (2006.01) G06F 11/10 (2006.01)

Patent

CA 1323442

ABSTRACT A fault-tolerant digital data processing system comprises at least a first input/output controller communicating with at least one peripheral device over a peripheral device bus. The peripheral bus includes first and second input/output buses, each having means for carrying data, address, control, and timing signals The input/output controller includes an element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The input/output controller further includes a bus interface element for receiving, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses.

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