Digital data processor with systolic array of pipelined...

Details Digital data processor with systolic array of pipelined... Digital data processor with systolic array of pipelined...

G - Physics

06

F

354/182

G06F 7/52 (2006.01) G06F 15/80 (2006.01) G06F 17/15 (2006.01)

Patent

CA 1226951

ABSTRACT A digital data processor is provided to multiply data elements by coefficients. It includes a systolic array of cells consisting of nearest neighbour connected gated full adders. The cells multiply data bits received from laterally adjacent cells and subsequently pass them on. The product is added to a cumulative sum bit from a cell above and to a carry bit recirculated from an earlier compu- tation. The output is passed to a cell below, and a new carry bit is recirculated for addition in a subsequent computation. Data and coefficients are input in counterflow to opposite sides of the array. An adder tree accumulates non-simultaneously computed contributions to individual output terms. The tree incorporates a delay and switches arranged to implement or bypass the delay according to earlier or later computation of a contribution. By virtue of this accumulation, the processor provides reduced cell redundancy compared to the prior art.

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