H - Electricity – 03 – M
Patent
H - Electricity
03
M
325/50, 340/75
H03M 13/00 (2006.01) H04B 7/26 (2006.01) H04L 1/00 (2006.01) H04Q 7/10 (2006.01)
Patent
CA 1225713
PHB. 32.960 11 ABSTRACT: In digitally encoded data transmission systems such as paging systems using a code word format, such as POCSAG, each code word includes a number of bits collec- tively termed the cyclic redundancy check bits. In a paging receiver the cyclic redundancy check bits are used to determine if there are errors in the received message code words. If an error is detected then one bit random error correction is generally applied because it has a more acceptable falsing rate compared to say two bit random error correction or four bit burst error correction. In a POCSAG paging system deseribed as an example the option of one bit random error correction or 4 bit burst error correc- tion with additional protection against falsing is given. The additional protection is to include error detection check bits in the entire message which is transmitted by the base station without deteriorating the calling rate performance. At the receiver any errors in the message code words are subjected to four bit burst error correction and thereafter the entire "corrected" message is subjected to a further check using the error detection check bits. Whether or not error detection check bits have been included in the message is indicated by preconditioning the message, for example by using predetermined ones of the plurality of addresses allocated to each pager for different purposes.
448080
Mabey Peter J.
Sharpe Anthony K.
Koninklijke Philips Electronics N.v.
Van Steinburg C.e.
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