Digital demodulator for phase shift keyed signals

Details Digital demodulator for phase shift keyed signals Digital demodulator for phase shift keyed signals

H - Electricity

04

L

329/11

H04L 27/22 (2006.01) H04L 27/233 (2006.01)

Patent

CA 1120559

CM-78876 DIGITAL DEMODULATOR FOR PHASE SHIFT KEYED SIGNALS Abstract A digital demodulator for differential phase shift keyed (DPSK) signals includes two pairs of 1-bit integrators for continuously taking the phase difference between successive DPSK bits. Each DPSK bit is subdivided into a plurality of bits, for example 15 bits. A weighted output signal having 4 bits is provided by each 1-bit integrator for each of the bits corresponding to a DPSK bit. The weighted output signals from each pair of 1-bit integrators are sine weighted and multiplied. The products are then added together for application to a comparator. The comparator compares the sum of the addition to a predetermined reference signal and provides a demodulated digital signal having a logical state dependent on whether the sum is greater or smaller than the predetermined reference signal.

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