Digital demodulator with frequency and timing control

Details Digital demodulator with frequency and timing control Digital demodulator with frequency and timing control

H - Electricity

04

L

H04L 27/22 (2006.01) H04L 7/033 (2006.01) H04L 7/04 (2006.01) H04L 27/227 (2006.01) H04L 27/233 (2006.01) H04L 7/08 (2006.01)

Patent

CA 2152781

A PSK signal is received and digitized in a limiter (26) to substantially remove the signal's amplitude characteristics. A phase detector (44) receives the digital data and, based upon transitions in the data between high and low states, provides phase estimates. The phase estimates are converted by a data decoder (50) into binary data representing the symbols transmitted to form the PSK signal. A number of overlapping windows of digital data are used to determine phase estimates. A unique word detector (52) receives binary data from the data decoder (50) and, using a correlation technique, identifies one set of windows which substantially maximizes synchronization of the demodulator with the received PSK signal. After the synchronizing window has been identified, an automatic frequency controller (46) monitors any frequency drift of the PSK signal and corrects the phase estimates.

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