Digital error measuring circuit for shading and registration...

H - Electricity – 04 – N

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350/1, 350/42

H04N 9/04 (2006.01) H04N 9/093 (2006.01) H04N 5/217 (2006.01)

Patent

CA 1162295

ABSTRACT OF THE DISCLOSURE To provide measurement of horizontal and vertical spatial errors, as well as shading errors, the active video picture is divided horizontally into 13 equal blocks, and vertically into 14 bands of checkers. During the setup mode, the signal from a selected camera is fed to an A/D converter in the video signal path, and to sync and pattern validation circuits which provide control and timing signals and an electronic test pattern. Horizontal error measure- ment is provided via a horizontal adder/memory loop whereby selected samples within the blocks of successive horizontal lines are selectively summed to provide successive pairs of summed horizontal digital data. Vertical error measurement is done simultaneously by a vertical adder/memory circuit whereby selected adjacent samples of alternate checkers are selectively delayed and added, to provide successive pairs of summed vertical digital data. During a read cycle, the horizontal and vertical pairs of digital data are selec- tively subtracted to inherently cancel the effects of existing shading errors, blooming, crosstalk, etc., and the difference signals are D/A converted. The horizontal and vertical transition and zero crossing information is estab- lished, and the transitions are compared with the electronic test pattern to derive the digital horizontal and vertical spatial error data for storage in a microprocessor memory. Shading error data are provided from the vertical adder/ memory circuit and also are stored in the microprocessor memory. The stored error data are subsequently retrieved and used to provide spatial and shading correction during the camera operating mode.

374867

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