Digital fractional clock divider

Details Digital fractional clock divider Digital fractional clock divider

H - Electricity

03

K

H03K 5/00 (2006.01) H03B 27/00 (2006.01) H03K 23/00 (2006.01)

Patent

CA 2538959

There is provided an apparatus comprising a multiphase clock generator, a frequency divider and a frequency synthesizer. The multiphase clock generator produces a plurality of phase shifted clock signals of frequency f, and having different phases relative to each other. The frequency divider receives the phase shifted clock signals of frequency f produces phase shifted clock signals of frequency f/N, where N is an integer. The phase shifted clock signals of frequency f/N have different phases relative to each other. The frequency synthesizer receives the phase shifted clock signals of frequency f/N and produces at least one clock signal of frequency f/ (N/2P), where P is an integer. A clocked sequential network comprising a sequential subcircuit including an initial sequential logic block and an end sequential logic block, and a multi-phase clock generator, is also provided. The multiphase clocked generator outputs a reference clock signal at a reference frequency f and a phase delayed clock signal at a delayed phase compared to the reference clock signal. The reference clock signal is received by the initial sequential logic block of the sequential subcircuit and the phase delayed clock signal is received by the end sequential logic block of the sequential subcircuit.

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