Digital frame synchronizer

Details Digital frame synchronizer Digital frame synchronizer

H - Electricity

04

J

363/13, 340/165

H04J 3/07 (2006.01)

Patent

CA 1323675

DIGITAL FRAME SYNCHRONIZER Abstract A desired positive fractional stuffing ratio is obtained in a frame synchronizer for a digital signal having a channel frame format that included two stuffing bit positions to obtain either positive or negative stuffing. The fractional stuffing ratio is obtained by controllably increasing the duration of a first predetermined number (p) of intervals during which data bits are written into the synchronizer and, then, by controllably decreasing the duration of a second predetermined number of intervals (q-p) during which data bits are written into the synchronizer. A data bit (D) is forced to be included in one of the stuffing bit positions occurring during each of the first predetermined number (p) of intervals and a non-data bit (X) is forced to be included in one of the stuffing bit positions occurring during each of the second predetermined number (q-p) of intervals.

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