Digital key telephone set and digital key telephone system

Details Digital key telephone set and digital key telephone system Digital key telephone set and digital key telephone system

H - Electricity

04

M

H04M 11/06 (2006.01) H04M 9/00 (2006.01) H04L 7/04 (2006.01)

Patent

CA 2356091

A clock generating circuit generates a clock of a rate corresponding to a Dch rate in response to a specification from the exterior. A counting circuit detects completion of reception of one frame by counting the clock number up to "11" at timing at which a start bit detecting circuit detects a start bit in a serial signal. An S/P converting circuit fetches a serial Dch signal bit by bit in synchronism with the clock, outputs the latest fetched 10 bits in a parallel form and latches eight bits of a real data portion among the output data into a latch circuit at the time when reception of one frame is completed. In parallel with the above operation, a parity calculating circuit and flag/interruption generating circuit set various flags and generate a reception completion interruption.

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