Digital loop carrier system having programmable timeslot and...

H - Electricity – 04 – J

Patent

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363/10

H04J 3/16 (2006.01) H04J 3/24 (2006.01)

Patent

CA 1310437

ABSTRACT OF THE DISCLOSURE A system for allocating a plurality of channel units to a transmission line having a plurality of timeslots including bandwidth and multiple time slot allocation. The system has a counter and a parallel to serial register for providing a channel address via an address signal corresponding to a predetermined one of the plurality of timeslots to each of the channel units. A processor is provided for assigning an assigned address to each channel unit of the plurality of channel units, such channel unit being assigned to a different selected timeslot of the plurality of timeslots. Each of the channel units has a comparator for comparing the channel address in the address signal to the assigned address, the channel unit upon having a correspondence between the channel address and the assigned address, transmitting and receiving on the transmission line. A bus connects the plurality of channel units to the means for addressing. An active channel unit can retain control of the transmission line for bandwidth and multiple time slot allocation.

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