Digital loop synchronization circuit

Details Digital loop synchronization circuit Digital loop synchronization circuit

H - Electricity

04

L

340/87

H04L 7/00 (2006.01) H04J 3/06 (2006.01) H04L 12/42 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 1126833

BAXTER-1 13. DIGITAL LOOP SYNCHRONIZATION CIRCUIT Abstract of the Disclosure There is disclosed a digital loop circuit for controlling synchronization around a closed loop communication system. The control circuit (20) is designed to automatically adjust the delay of the loop to maintain a constant frame bit length without regard to the number of stations connected into the loop. As stations are added or subtracted from the loop, the system operated to subtract or add delay as necessary. A first in and first out (FIFO) register having a bit capacity equal to the frame size is inserted serially in the loop and a separate clock is used to control the input and the output of the first in and first out register (FIFO). If a unique frame bit is not received in the anticipated position then the clock output skips one count per frame thereby adding delay to the loop. The loop control circuit operates for situations where the framing bit is on a separate channel and also when the framing bit is on the actual data channel. FIGURE 1

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