Digital multiplying circuit

Details Digital multiplying circuit Digital multiplying circuit

G - Physics

06

F

354/167

G06F 7/52 (2006.01)

Patent

CA 1219955

ABSTRACT OF THE DISCLOSURE There is provided a digital multiplying circuit in a parallel multiplying circuit which can multiply an input which changes at a high data rate by the pipeline processing. A multiplicand is inputted to this circuit. Partial product signal generating circuits of the number corresponding to only the number of partial product signals which are needed are provided. The partial product signal generating circuits produce the partial product signals in accordance with the state of predetermined bits of a multiplier. Each partial product signal is added, thereby obtaining a multiplication output of the multiplicand. The pipeline processing is performed in the adding operation of each partial product signal. The multiplier and multiplicand are delayed. The predetermined partial product signal generating circuits are arranged immediately before the adders which need the partial product signals, thereby obtaining the partial product. With this digital multiplying circuit, the total number of bits of registers is reduced and the circuit scale is made small.

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