Digital phase aligner and method for its operation

Details Digital phase aligner and method for its operation Digital phase aligner and method for its operation

H - Electricity

04

J

H04J 3/06 (2006.01) H03L 7/081 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2001266

In methods and apparatus for aligning the phase of a local clock signal with the phase of a data signal, an incoming data signal is delayed to provide a delayed data signal and regenerated with a local clock signal to provide a regenerated data signal. A difference between the phase of the delayed data signal and the phase of the regenerated data signal is detected. The phase of the local clock signal is retarded by a predetermined fraction of a bit period if the regenerated data signal leads the delayed data signal and is advanced by the predetermined fraction of the bit period if the regenerated data signal lags the delayed data signal. The retiming, detecting, retarding and advancing steps are repeated continuously to obtain and maintain approximate alignment of the phase of the local clock signal with the phase of the delayed data signal. The methods and apparatus are useful in high speed packet switches.

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