Digital phase lock loop for clock signal recovery

Details Digital phase lock loop for clock signal recovery Digital phase lock loop for clock signal recovery

H - Electricity

03

L

H03L 7/10 (2006.01) H03L 7/099 (2006.01) H04J 3/07 (2006.01)

Patent

CA 2204275

The invention involves a phase lock loop supplying a clock signal recovered from a reference clock signal Fref without transitions. It comprises: - an initial M frequency divider that receives the clock signal and supplies a signal at frequency Fref/M; - a phase comparator that supplies a phase error signal from the Fref/M frequency signal and the output of a second M frequency divider; - a K frequency divider supplying a signal at frequency Fk from a local oscillator operating at frequency FLO and receiving as a control signal the phase error signal; - a p/q division ratio adder/accumulator receiving the local oscillator signal at frequency FLO and supplying a signal at frequency FO equal to FLO*p/q; - a mixer supplying a signal at frequency Fn equal to FO-Fk from the signals at frequencies Fk and FO; - an N frequency divider synchronized by FLO receiving the signal at frequency Fn and supplying the recovered clock signal to the second M frequency divider.

L'invention concerne une boucle à verrouillage de phase fournissant un signal d'horloge récuperée à partir d'un signal d'horloge de référence Fref danslequel des transitions sont absentes. Elle comporte: - un premier diviseur de fréquence par M recevant l'horloge Fref et fournissant un signal de frequence Fref/M; - un comparateur de phase fournissant un signal d'erreur de phase à partir du signal de fréquence Fref/M et du signal de sortie d'un deuxième diviseur de frequence par M; - un diviseur de fréquence par K fournissant un signal de frequence Fk à partir d'un signal d'oscillateur local de frequence FOL recevant comme signal de commande le signal d'erreur de phase; - un additionneur-accumulateur de rapport de division p/q recevant le signal d'oscillateur local de frequence FOL et fournissant un signal de fréquence F0 égal à FOL*p/q; - un mélangeur fournissant un signal de fréquence Fn égal à F0-Fk à partir du signal de fréquence Fk et du signal de fréquence F0; - un diviseur de fréquence par N synchronisé par FOL recevant le signal de fréquence Fn et fournissant l'horloge récupérée au deuxième diviseur de fréquence par M.

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