H - Electricity – 03 – L
Patent
H - Electricity
03
L
H03L 7/18 (2006.01) H04J 3/07 (2006.01)
Patent
CA 2126163
- 19 - ABSTRACT DIGITAL PHASE LOCKED LOOP ARRANGEMENT A digital phase locked loop arrangement is used in a desynchronizer demapping a plesiochronous stream from a synchronous bitstream is disclosed to remove jitter due to overhead gapping from the plesiochronous stream. To this end the part of the synchronous bitstream constituting the plesiochronous stream is written into a buffer memory (BUFF), the write address (WRADDR) of which is incremented at the rate of this plesiochronous part. The read address (RDADDR) for the buffer memory (BUFF) is derived from the write address (WRADDR) in the digital phase locked loop arrangement. Herein, a negative feedback for byte justifications in the synchronous bitstream and a positive feedback for bit justifications therein is provided so that byte justifications give rise to a lower change in the incrementing rate of the read address (RDADDR) but of longer duration, whereas bit justifications give rise to an increased change in this incrementing rate but of shorter duration.
de Langhe Marc Robert Francois
Haspeslagh Johan Joseph Gustaaf
Reusens Peter Paul Frans
Van Hoogenbemt Stefaan Margriet Albert
Alcatel N.v.
Robic
LandOfFree
Digital phase locked loop arrangement does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital phase locked loop arrangement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital phase locked loop arrangement will most certainly appreciate the feedback.
Profile ID: LFCA-PAI-O-1603769