Digital phase-locked loops

Details Digital phase-locked loops Digital phase-locked loops

H - Electricity

03

L

328/28, 331/35

H03L 7/08 (2006.01) H03L 7/091 (2006.01) H04N 9/455 (2006.01) H04N 17/02 (2006.01)

Patent

CA 1277724

Abstract A clock signal having a predetermined phase relationship relative to a signal element of an analog signal that repeats at a nominally fixed frequency is generated by an oscillator having an oscillation frequency that depends on the value of a control signal. The input analog signal is sam- pled under control of the clock signal, and a succession of digital words representing the ampli- tudes of the successive samples is generated. The digital words are written into memory, and are digitally analyzed in order to determine the phase, within the cycle of the clock signal, of the signal element. The signal that represents the phase of the signal element relative to the clock signal is used as a control signal for controlling the fre- quency of oscillation of the oscillator.

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