Digital processor for convolution and correlation

Details Digital processor for convolution and correlation Digital processor for convolution and correlation

G - Physics

06

F

354/141

G06F 17/15 (2006.01) G06F 15/80 (2006.01) G06F 11/00 (2006.01) G06F 11/20 (2006.01)

Patent

CA 1263757

ABSTRACT A digital processor is provided for performing an N-point convolution or correlation of q-bit coefficients with data words guard band extended to p bits. The processor includes an array of one-bit clock- activated gated full adder cells arranged in N rows and q columns. Each cell is arranged to input data> carry and cumulative sum bits and to output the data bit and new carry and cumulative sum bits corres- ponding to the product of the input data bit with a respective stationary coefficient bit. The output carry bit is recirculated on the respective cell. Cumulative sum generation is cascaded down array columns. Data moves along each row and thence to the next lower row via delaying means providing a delay appropriate for correct partial product formation. Data is input bit and word serially to a first row cell and thereafter moves along successive rows progressively further down the array. Sums of partial products output by the array are accumulated according to bit significance by an accumulator device arranged to accumulate successive convolution or correlation results in different adding means. This avoids erroneous addition of contri- butions to different results. The array is cascadable to provide larger processors. Cascaded arrays may be arranged to be fault tolerant, and a faulty array may be bypassed without operating speed penalties arising from bypass lines.

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