Digital processor for two's complement computations

Details Digital processor for two's complement computations Digital processor for two's complement computations

G - Physics

06

F

G06F 7/544 (2006.01) G06F 15/76 (2006.01) G06F 15/80 (2006.01) G06F 17/16 (2006.01)

Patent

CA 2051404

2051404 9013867 PCTABS00002 A digital processor (10) for two's complement computations incorporates an array (12*) of multiplier cells (12) each having the one-bit gated full adder logic function. The array (12*) has nearest-neighbour connections (16, 18, 20) containing clock-activated latches (42, 44, 50) for bit propagation. On each clock cycle, the cells (12) receive input data, carry and cumulative sum bits. Each cell (12) adds the carry and cumulative sum bits to the product of the data bit and a respective coefficient digit associated with the relevant cell (12). Data bits pass along array rows and sum bits accumulate in cascade down array columns. Carry bits are recirculated. Each coefficient digit is expressed as a sign bit and at least one magnitude bit consisting of or including a level bit. Each cell (12) includes multiplicative gating means (58, 62) responsive to the sign and level bits, and carry feedback means (60, 66) responsive to a least significant data bit flag to substitute the sign bit for a carry feedback bit. Each coefficient digit may include an additional magnitude bit expressed as a shift bit and employed to select multiplicand data bit significance, the gating means (58, 62) being responsive to flag bits to eliminate unwanted sign extension bit products. The processor (10 or 200) may include accumulating means (14 or 214) incorporating gates (90, 98 or 292, 298, 336) responsive to flag bits and arranged to eliminate unwanted result sign extension bits.

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