Digital radio communication device

H - Electricity – 04 – L

Patent

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Details

H04L 27/00 (2006.01) H03K 9/00 (2006.01) H04B 17/00 (2006.01) H04L 1/00 (2006.01) H04L 1/06 (2006.01) H04L 1/20 (2006.01) H04L 25/03 (2006.01) H04L 27/01 (2006.01) H04L 27/22 (2006.01) H04L 27/227 (2006.01)

Patent

CA 2165815

Digital radio communication equipment which can prevent the worsening of the error rate of demodulated signals due to the equalization of the output from a digital demodulator (6) and can always receive radio waves in the optimum state regardless of the existence of delayed waves. A bit error rate estimation circuit (8) estimates a bit error based on demodulated serial data (S3) outputted from the circuit (6) and outputs the estimated results to a control circuit (20) as an estimated bit error signal (S5). The circuit (20) selects either the demodulated serial data (S3) outputted from the circuit (6) or the demodulated serial data (S4) from an equalizer (7) by switching a selector (9) in accordance with a selector control signal (S6) based on the signal (S6) from the circuit (8) and an electric field intensity indicating signal (S2) from a reception circuit (3), and then outputs the selected data as demodulated data (S7).

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