Digital repetition rate check circuit

Details Digital repetition rate check circuit Digital repetition rate check circuit

H - Electricity

03

K

328/159

H03K 3/64 (2006.01) G06F 11/00 (2006.01) H03K 5/19 (2006.01)

Patent

CA 1039366

DIGITAL REPETITION RATE CHECK CIRCUIT ABSTRACT OF THE DISCLOSURE A pulse repetition rate check circuit of the type which detects when the second of two consecutive pulses from a pulse generator is early or late with respect to a predeter- mined repetition time period. It includes an early pulse detec- tor, first and second early pulse detector enabling circuits and first and second clocks. Each early pulse detector enabling cir- cuit enables the early pulse detector responsive to its associ- ated clock for a predetermined time so that a second pulse occurring within the predetermined time is detected as an early second pulse. The early pulse detector enabling circuit includes an inhibit arrangement for preventing the enabling of the early pulse detector after it has been once enabled. A steering circuit alternately directs the clocking signals from an oscillator to the clocks responsive to alternate pulses and a clock reset ar- rangement associated with each clock causes each clock to be re- set responsive to the other clock to assure that one clock is always conditioned to act upon the receipt of the next pulse. The pulse repetition rate check circuit also includes first and second late pulse detectors which are coupled to the first and second clocks respectively for providing an error signal indicating that the second pulse is late should the second pulse fail to occur within the predetermined repetition time period.

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