Digital scaling circuitry with truncation offset compensation

Details Digital scaling circuitry with truncation offset compensation Digital scaling circuitry with truncation offset compensation

H - Electricity

04

N

350/81

H04N 5/21 (2006.01) G06F 7/48 (2006.01) H03H 17/04 (2006.01)

Patent

CA 1245345

Abstract of the Disclosure A scaling circuit for scaling PCM signals by factors less than one includes a bit-shift and truncating circuit. Roundoff error compensating circuitry adds an offset value to the samples to be scaled by the bit-shift circuitry to compensate for errors produced by truncation without rounding. The offset values are dithered to increase the apparent resolution of the system.

504418

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