Digital secondary clock

Details Digital secondary clock Digital secondary clock

G - Physics

04

C

58/0.5

G04C 3/00 (2006.01) G04C 17/00 (2006.01) G04G 7/00 (2006.01) G04G 9/00 (2006.01) G06F 17/00 (2006.01)

Patent

CA 1139573

PROGRAMMED DIGITAL SECONDARY CLOCK Abstract of the Disclosure A programmed digital secondary clock which functions as a master clock, a sub-master clock or a slave clock. When operating as a master clock, the programmed digital secondary clock maintains an updated real time count based on a 50 hz or 60 hz ac line or digital oscillator signal, displays the count, and serially transmits digital information representative of the updated real time count for use by a slave clock. When operating as a sub-master clock, the programmed digital secondary clock receives an hourly or twice-a-day correction signal from a conventional master clock or a conventional electronic receiver, corrects the real time count, displays the corrected count, and serially transmits digital information representative of the cor- rected real time count for use by a slave clock. Identical programmed digital secondary clocks can be connected in daisy chain. The first clock can operate as a master clock or as a sub-master clock. The following clocks can be operated as slave clocks. When operating as a slave clock, the programmed digital secondary clock synchronously receives serial digital information representative of real time every second, maintains an updated real time count based on the received information, displays the count, and serially transmits digital infor- mation representative of the real time count for use by a following slave clock. The programmed digital secondary clock can be operated as an elapsed timer or as an interval timer without interfering with the operation of the clock as a master, sub-master or slave clock. 1345 P/3 CA

329213

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