Digital signal clamp circuitry

Details Digital signal clamp circuitry Digital signal clamp circuitry

H - Electricity

04

N

350/83

H04N 5/57 (2006.01) H04N 5/18 (2006.01)

Patent

CA 2012809

A digital signal clamp circuit is realize using an adder and an up/down counter. The digital signal is coupled to one input of the adder and the counter output is coupled to a second input of the adder. The up/down counter is enabled to count only during signal intervals exhibiting the desired clamping level. The counter is controlled to count up or down depending on the polarity of the signal provided by the adder. The count value in the counter is continuously applied to the adder to provide clamping. Using a truncated count value from the counter enhances clamping performance.

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