Digital signal combining circuit for a diversity receiver,...

Details Digital signal combining circuit for a diversity receiver,... Digital signal combining circuit for a diversity receiver,...

H - Electricity

04

B

325/42

H04B 7/02 (2006.01) H04L 1/02 (2006.01)

Patent

CA 1130386

Abstract of the disclosure: A digital signal combining circuit for a diversity receiver for digital communication comprises buffer memories (16) for memorizing digital signal sequences produced by receiver units (11, 12), respectively, and an APC loop (26-39) for locking the phases of read-out clocks for simultaneously reading the memories to an averaged phase of the digital signal sequences, No code error appears in an output signal of the receiver provided that the phase difference between two of the digital signal sequences from which the output signal is selected, is less than m bit periods, where m represents the number of memory cells of each suffer memory.

342621

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