Digital signal multiplexing apparatus and demultiplexing...

H - Electricity – 04 – J

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363/17

H04J 3/06 (2006.01) H04J 3/04 (2006.01) H04J 3/16 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 2024809

A digital signal multiplexing apparatus has n (n is an arbitrary integer) multiplexing circuits (11-1n) for converting input signals from a plurality of lines into m (m is an arbitrary integer) parallel signals which are added with added bits and have a first transmission speed, a parallel-serial conversion circuit (40) for converting the m parallel signals from the n multiplexing circuits into a serial multiplexed signal by a parallel-serial conversion, and a bus (30) for connecting the n multiplexing circuits and the parallel-serial conversion circuit. The n multiplexing circuits respectively have a circuit for successively transmitting the m parallel signals to the bus using a pulse signal having a second transmission speed which is n times the first transmission speed. A digital signal demultiplexing circuit has a serial-parallel conversion circuit (75) for converting a serial input signal into m (m is an arbitrary integer) parallel signals having a predetermined transmission speed, n (n is an arbitrary integer) demultiplexing circuits (51-5n) for demultiplexing added bits from the m parallel signals from the serial-parallel conversion circuit (75) and for outputting the added bits on a plurality of lines with the predetermined transmission speed, and a bus for connecting the serial-parallel conversion circuit and the n demultiplexing circuit (75), and the n demultiplexing circuits respectively have a circuit for fetching the m parallel signals output on the bus from the serial-parallel conversion circuit with a clock timing of a speed identical to the predetermined transmission speed.

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