G - Physics – 06 – F
Patent
G - Physics
06
F
354/148
G06F 15/00 (2006.01) G06F 7/575 (2006.01) G06F 9/32 (2006.01) G06F 9/345 (2006.01) G06F 9/38 (2006.01) G06F 13/28 (2006.01) G06F 15/78 (2006.01)
Patent
CA 1288169
ABSTRACT OF THE DISCLOSURE A digital signal processor of a simple circuit configu- ration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal proces- sor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.
568527
Kameyama Masatoshi
Kamizawa Koh
Katoh Yoshiaki
Kinjo Naoto
Murakami Tokumichi
Kirby Eades Gale Baker
Mitsubishi Denki Kabushiki Kaisha
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