Digital signal processor with coupled multiply-accumulate units

Details Digital signal processor with coupled multiply-accumulate units Digital signal processor with coupled multiply-accumulate units

G - Physics

06

F

G06F 7/544 (2006.01)

Patent

CA 2400647

Two multiply-accumulate units are coupled together so that the computation (B*C)+(D*E) can be completed in one cycle. An adder (216) adds together the products of the two multipliers (206), (208). The sum is applied to the first accumulator (220). Preferably, the second product is also applied to the second accumulator (222), and a multiplexer (218) applies either a zero or the second product to the adder (216). If two unrelated computations are to be executed simultaneously, then the zero is applied, and the output of the second accumulator is fed back to the register file (PI2). If a single (B*C) + (D*E) computation is to be executed, then the second product is applied to the adder, and the output of the second accumulator is disregarded.

Selon l'invention, deux multiplicateurs-accumulateurs sont couplés de sorte que le calcul (B*C)+(D*E) puisse s'effectuer en un cycle. Un additionneur (216) additionne les produits des deux multiplicateurs (260), (208). La somme de ces multiplicateurs est appliquée au premier accumulateur (220). De préférence, le second produit est également appliqué au second accumulateur (222) et un multiplexeur (128) applique soit un zéro, soit le second produit à l'additionneur (216). Si deux calculs indépendants doivent être effectués simultanément, c'est le zéro qui est appliqué et la sortie du second accumulateur est retournée à la pile de registres (PI2). Si un seul calcul (B*C) + (D*E) doit être effectué, c'est le second produit qui est appliqué à l'additionneur et la sortie du second accumulateur n'est pas prise en compte.

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