Digital suppressed clock recovery circuit

Details Digital suppressed clock recovery circuit Digital suppressed clock recovery circuit

H - Electricity

03

K

328/87

H03K 5/00 (2006.01)

Patent

CA 1189578

ABSTRACT OF THE DISCLOSURE A digital suppressed clock recovery circuit for use in a baseband communication, recorded data recovery and other digital modulation means is disclosed which applies a clock- window filter permitting same number of transitions of feed- back signal as the input modulated signal, a digital frequency/ phase comparator comparing the input signal and the filtered feedback signal for producing a digital compensation signal and a digitally controlled digital oscillator receiving the said compensation signal for producing a variable frequency source output. This frequency source is further averaged by a counter for producing the recovered data clock output. This data clock is also fed back to the clock-window filter as the feedback signal.

430512

Affiliated with

Also associated with

Rating

Digital suppressed clock recovery circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital suppressed clock recovery circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital suppressed clock recovery circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1327390