Digital-to-analog converter

B - Operations – Transporting – 41 – F

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354/102

B41F 33/04 (2006.01) H03M 1/00 (2006.01)

Patent

CA 1275737

ABSTRACT: The currents (I3, I4, I5) of first current- source transistors (T3, T4, T5) constitute a binary weighted series of currents, which currents are each in a given ratio to a current (I1) which is applied to a reference transistor (T1). The currents (I3, I4, I5) from the first current-source transistors (T3, T4, T5) are switched to the analog output (15) or to the positive power-supply terminal (20) by means of first switching devices (3.1, 3.2, 3.3). The converter further comprises a contxol device (30), which comprises a second current- source transistor (T8), which is connected to a refer- ence-current source (2) or to the positive power-supply terminal (20) by means of a second switching device (4). The current (I8) from the second current-source transis- tor (T8) has a given ratio to the current (I1) in the reference transistor (T1). If the second current-source transistor (T8) is connected to the positive power-supply terminal (20), the reference transistor (T1) will carry the full reference current (Iref) from the reference cur- rent source (2), and if the second current-source tran- sistor (T8) is connected to the reference current source (2) the reference transistor (T1) will carry only a frac- tion of the reference current (Iref). As the currents (I3, I4, I5) from the first current-source transistors (T3, T4, T5) are in a given ratio to the current (I1) in the reference transistor (T1), these currents (I3, I4, I5) are a similar fraction smaller in the first case than in the second case. By increasing the current (I1) in the reference transistor (T1) stepwise from a fraction to the full reference current (Iref) over the range of the digi- tal input code, the output current range of the converter will also vary stepwise.

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