Digital to analog converter with system gain insensitivity

G - Physics – 01 – B

Patent

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Details

354/83, 340/137.

G01B 7/00 (2006.01) G05D 3/20 (2006.01) H03M 1/00 (2006.01)

Patent

CA 1056478

ABSTRACT OF THE DISCLOSURE A position-measuring system is disclosed in which an improved digital to analog converter accepts an error signal from a position measuring transducer such as an Inductosyn? transducer, the error signal being processed to be a digital signal representation of the magnitude and two-state direction of a positional error. The digital signal is converted into analog signals representative of trigonometric functions of a command position of the transducer for tans- mission to the transducer in a closed loop system. The im- proved converter takes the two-state digital input signal and changes the command position by a predetermined value whenever the error signal changes from one to another of its two direc- tion states. This change in the command position causes the system to operate as if the error signal input had three-states two directional states and an intermediate "dead zone". The in- sensitivity to system gain inherent with a two-state error input is maintained, while at the same time the system stability of a three-state error input (with dead zone) is achieved. The counter operates by counting down clock pulses through two parallel counters which have a count difference proportional to the error input. The counter outputs are logically combined to produce pulse-width modulated analog signals having fundamental component amplitudes which are trigonometric functions of the command position. In the described embodiment the aforementioned change in command position on a directional transition of the error signal is obtained by delaying the output of one of the two counters by a fixed period equal to 1.3 bit periods of the clock source whenever the error signal switches from a first to a second of its two directional states and removing that delay whenever the error signal changes from the second to the first of said states. Special circuitry is also provided for decreasing the sampling rate of the error signal whenever the error signal is in a transitional phase, i.e., when it has not remained in one directional state for a predetermined time. The decreased sampling rate increases the reliability and stability of the position measuring system. Also disclosed is improved and simplified circuitry for generating the two counter output signals so that phase walk between those counter outputs and a standard reference counter output is eliminated.

253669

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