Digitally controlled delay circuit

Details Digitally controlled delay circuit Digitally controlled delay circuit

H - Electricity

03

K

328/92

H03K 5/13 (2006.01) H03K 5/00 (2006.01)

Patent

CA 1271816

DIGITALLY CONTROLLED DELAY CIRCUIT Abstract A first inverter circuit is coupled between a first voltage source and a reference potential by a plurality of cascaded transistors. Each of the cascaded transistors has a control gate which may be selected to bring the resistance of the transistor into circuit with the inverter circuit to control the charging rate of a distributed capacitance. An output circuit coupled to the first inverter circuit provides the distributed capacitance and an inverted buffered output. The output circuit also includes an output which may be connected to another circuit of the present invention to form a cascaded delay circuit and to receive a reset signal for resetting the cascaded delay circuit.

551902

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