Digitally controlled phase shifter

Details Digitally controlled phase shifter Digitally controlled phase shifter

H - Electricity

03

K

H03K 5/13 (2006.01) H03L 7/08 (2006.01) H03L 7/081 (2006.01) H04J 3/06 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2130268

A clock is phase shifted by an amount controlled by the value of a control signal by establishing at least several discrete delay times to be imposed on the clock. The control signal value controls selection of the imposed discrete delay time. An analog-to-digital converter of a phase locked loop responds to intelligence representing variable phase bits and the selected phase shifted clock to control the signal value. The selected replica is derived by at least several cascaded substantially equal time delay units. In one embodiment, a multiplexer responds to the clock and the signal value, with is Gray coded, to control connections from one of the delay units to an output terminal. In another embodiment, the number of cascaded delay units interposed between the clock and an output terminal is controlled by the signal value. One use of the phase shifter is in a phase lock loop.

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