Direct coupled fet logic

Details Direct coupled fet logic Direct coupled fet logic

H - Electricity

03

K

328/128

H03K 17/13 (2006.01) H03K 17/687 (2006.01) H03K 17/78 (2006.01) H03K 19/0185 (2006.01) H03K 19/0952 (2006.01)

Patent

CA 1264825

DIRECT COUPLED FET LOGIC Abstract of the Disclosure A direct coupled FET logic (DCFL) circuit element has an active FET with source connected to a low reference voltage and drain connected through a pull-up FET to a higher reference voltage. An input is applied to the gate of the active FET and the output is taken from its drain, the pull-up FET having its gate connected to its source. In depletion mode configuration, a photodiode is connected to the gate of the active FET, the photodiode energizable to downwardly shift the gate voltage. In enhancement mode configuration, a photodiode is connected between source and gate of the pull-up transistor and is energized to shift the gate voltage upwardly. The photodiodes are integrated with the active and pull-up FETs and are energized by light or decay radiation.

532354

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