Direct memory access controller

Details Direct memory access controller Direct memory access controller

G - Physics

06

F

354/230.84

G06F 13/20 (2006.01) G06F 13/16 (2006.01) G06F 13/28 (2006.01)

Patent

CA 1218161

Abstract of the Disclosure An arrangement to couple at least one I/O device to the main bus between a CPU and a main memory in a digital computer system is shown to include a random access memory made up of a dedicated part of the main memory and control circuitry to allow access between addresses in the random access memory and either the CPU or the at least one I/O device, such circuitry being arranged to give priority of access to the CPU except when data is actually being transferred from the I/O device and the random access memory.

471896

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