Distributed cache dram chip and control method

Details Distributed cache dram chip and control method Distributed cache dram chip and control method

G - Physics

11

C

352/81

G11C 11/24 (2006.01) G06F 12/02 (2006.01) G06F 12/08 (2006.01) G11C 7/00 (2006.01)

Patent

CA 2011518

ABSTRACT OF THE DISCLOSURE A computer memory subsystem is comprised of one or more Dynamic Random Access Memory (DRAM) arrays with on-chip sense latches for storing data outputted from the DRAM, an on-chip Static Random Access Memory (SRAM) functioning as a Distributed Cache and an on-chip multiplexor. A first data bus interconnects the sense latches, the SRAM and the multiplexor. A second data bus interconnects the multiplexor and the SRAM. A memory controller generates signals which cause information to be extracted from the DRAM while the contents of the SRAM is unchanged or vice versa.

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