Distributed cache in dynamic rams

Details Distributed cache in dynamic rams Distributed cache in dynamic rams

G - Physics

06

F

354/241

G06F 12/08 (2006.01) G11C 7/00 (2006.01) G11C 11/34 (2006.01)

Patent

CA 1233272

ABSTRACT DISTRIBUTED CACHE IN DYNAMIC RAMS A microcomputer memory system is organized into a plurlaity of banks (16). Each bank consists of an array of static column mode dynamic random access memories (DRAMs) of 5 the type having an on-chip static buffer for storing an entire row. The static buffers associated with each bank functions as a distributed cache (24) to hold the last accessed row for the associated bank. A memory controller (18) receives real addresses from a CPU (15) or other device on the memory bus (14) and extracts bank and row numbers from the address. The memory controller determines whether the accessed row for a memory bank is in the distributed cache and, if it is, accesses the distributed cache for that bank. Otherwise, the memory controller switches the 5 contents of the distributed cache with the contents of the addressed row for that bank.

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