H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/128, 356/149
H01L 29/76 (2006.01) H01L 29/08 (2006.01) H01L 29/10 (2006.01) H01L 29/417 (2006.01)
Patent
CA 1243130
DISTRIBUTED FIELD EFFECT TRANSISTOR STRUCTURE Abstract of the Disclosure A field effect transistor (FET) structure (10) suitable for MOS and CMOS IC fabrication processes includes spaced apart alternating source and drain regions (14, 15) distributed in a rectangular checkerboard pattern of horizontal and vertical rows. A first grid (16) of intersecting horizontal and vertical conductive gate lines (16a, 16b) overlaps adjacent source and drain regions (14, 15) of the array and is dielectrically isolated from the source and drain regions by an insulating layer. The horizontal and vertical gate lines (16a, 16b) provide a single gate element distributed across the array which reduces FET channel length and channel resistance. A second grid comprising a set of parallel diagonal alternating source lead lines (22) and drain lead lines (24) is dielectrically isolated from from the first grid. The source lead lines (22) are electrically coupled to source regions (14) and the drain lead lines (24) are electrically coupled to drain regions (15). The second grid includes a first metal layer (25) of lower diagonal lead lines and a second metal layer (26) of upper diagonal lead lines overlying at least a portion of the lower diagonal lead lines of the first metal layer. The first and second metal layers (25, 26) are selectively coupled to reduce current density and resistance in the source and drain diagonal lead lines (22, 24) without increasing the width of the lead lines. Back contact areas or regions (35) are distributed around the perimeter of the checkerboard pattern forming a back contact guard ring or band.
519693
Fairchild Semiconductor Corporation
Smart & Biggar
LandOfFree
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