Dma controller

Details Dma controller Dma controller

G - Physics

06

F

G06F 13/16 (2006.01) G06F 13/28 (2006.01) G06F 13/42 (2006.01)

Patent

CA 2172942

Address generators output addresses of transfer data of transfer origin and destination DRAM's. Updating of the transfer addresses from the address generators during execution of DMA is performed based on a CAS signal from a timing signal generator. A delay element delays the CAS signal by a time which is the sum of an access time of the transfer origin DRAM and a data set-up time of the transfer destination DRAM. A transfer data counter counts the number of leading edges of the CAS signal while a RAS signal from the timing signal generator is held active. When a counted value reaches a preset value, the transfer data counter outputs continuous data transfer suspension information to the timing signal generator. With this arrangement, the halt in operation of a CPU due to continuous occupation of a bus is effectively prevented while achieving the increased data transfer rate.

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