Double data rate flip-flop

Details Double data rate flip-flop Double data rate flip-flop

H - Electricity

04

J

H04J 3/04 (2006.01) H03K 17/62 (2006.01)

Patent

CA 2432308

Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.

L'invention concerne un procédé et un appareil permettant de doubler la vitesse de rendement de la transmission de données sur un trajet logique consistant à apporter deux circuits à verrouillage qui reçoivent en alternance des bits successifs d'un flot de données à transmettre et un multiplexeur ayant des trajets de transmission de données qui sont synchronisés par deux horloges distinctes, horloges qui sont sensiblement déphasées sur 180 degrés.

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