Double stage sense amplifier for random access memories

G - Physics – 11 – C

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330/26, 352/81

G11C 7/06 (2006.01) G11C 8/16 (2006.01)

Patent

CA 1309148

FR 9 87 013 ABSTRACT DOUBLE STAGE SENSE AMPLIFIER FOR RANDOM ACCESS MEMORIES In combination with an electronic memory of the type having a plurality of memory cells (CA, ... CN) connected between two bit lines (BLT, BLC) having inherent bit line capacitances (C1, C2), there is disclosed an improved sense amplifier (15) comprised of two stages. A first stage (16) includes a first clocked latch (5) having an enable device (T5), gated by a first control signal (SSA) and bit switches (T6, T7) connected between the common nodes (6, 7) of said first clocked latch and said bit lines, and gated by a bit switch control signal (BS) to provide an output signal on first data lines (DLT, DLC). A second stage (17) includes a second clocked latch (20) having an enable device (T24) gated by a second control signal (SL) and data switches (T28, T29) connected between second data lines (DT, DC) at the same potential as data output nodes (21, 22) of said second clocked latch and said first data lines (DLT, DLC). Said data switches (T28, T29) are gated by a data switch control signal (DS) which is derived from the bit switch control signal (BS), so that said first and second stages (16, 17) operate sequentially to amplifly the data continuously along the sensing chain of the data path during a READ operation to provide a data output signal on said data output nodes. The data is then available for furhter processing at the output terminal (24) of the output driver (23). Fig. 2

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