Dram cell having increased data retention time

Details Dram cell having increased data retention time Dram cell having increased data retention time

G - Physics

11

C

G11C 11/401 (2006.01) G11C 11/405 (2006.01) H01L 27/11 (2006.01)

Patent

CA 2342517

A planar 4T-2C DRAM memory cell which balances leakage to a first order to increase the data retention time is disclosed. The memory cell of the present invention uses MOS capacitors as load devices for a cross-coupled pair of pull-down transistors, instead of TFT transistors, pmos transistors or high resistive poly which have been used in similar circuits of the prior art. More specifically, the tunnelling current through the thin gate oxide of the MOS capacitors is used as the load for the cross-coupled devices. The cross-coupled transistors and the access transistors have thicker gate oxides in order to minimize their leakage. The resulting layout of the memory cell of the present invention has a 30 percent smaller area than the area of a conventional 6T SRAM memory cell. Data retention time in the memory cell of the present invention is about 10 times longer than previous 4T DRAM cells.

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