Dram mapping for a digital video decompression processor

Details Dram mapping for a digital video decompression processor Dram mapping for a digital video decompression processor

H - Electricity

04

N

H04N 7/50 (2006.01) G06T 9/00 (2006.01) H04N 7/26 (2006.01)

Patent

CA 2154856

A random access memory of a digital video decompression processor is mapped to enable the reconstruction of successive video frames of pixel data represented by a compressed video bitstream. A FIFO buffer is provided in the RAM for the compressed video bitstream. A first luminance anchor frame buffer and a first chrominance anchor frame buffer are provided for storing a full frame of luminance data and a full frame of chrominance data for a first anchor frame used to predict B- frames. A second luminance anchor frame buffer and second chrominance anchor frame buffer are provided for storing a full frame of luminance data and a full frame of chrominance data for a second anchor frame used to predict the B-frames. A first B-frame luminance buffer is provided in the RAM and sized to store less than 100% of the amount of luminance data in a first B-frame field. A second B-frame luminance buffer is provided in the RAM and sized to store at least 100% of the amount of luminance data in a second B-frame field. A B-frame chrominance buffer is provided in the RAM to store at least 100% of the amount of chrominance data in a B-frame. The anchor frames and B-frames are read from the RAM to enable the reconstruction of successive video frames. The memory mapping is particularly well suited for the decompression of PAL formatted video in an MPEG-2 decoder.

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