Dual byte order computer architecture

Details Dual byte order computer architecture Dual byte order computer architecture

G - Physics

06

F

354/230

G06F 15/76 (2006.01) G06F 7/76 (2006.01) G06F 12/04 (2006.01)

Patent

CA 1285075

ABSTRACT A CPU or other function unit is disclosed which follows one data ordering scheme internally, and in which incoming and/or outgoing data pass through a data order conversion unit for adapting it to a selectable external data ordering scheme. The means for specifying the external data ordering scheme is accessible from outside the physical package(s) in which the functional unit is housed. The data order conversion unit may comprise a load aligner and/or a store aligner, one or both of which may comprise means for shifting informational unit of a smaller size within informational units of a larger size. The shift amount may derive from the low order address bits and may be altered depending on the external data ordering means selected.

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