Dual framing bit sequence alignment apparatus and method

Details Dual framing bit sequence alignment apparatus and method Dual framing bit sequence alignment apparatus and method

H - Electricity

04

L

354/67

H04L 9/00 (2006.01)

Patent

CA 2029248

ABSTRACT A dual-framing-bit-alignment apparatus having a communications channel, a data device, an encryptor, a framing-bit device, a decryptor, a first framing-bit repositioner, and a second framing-bit repositioner. The first data device generates a first data-bit sequence having a first framing-bit sequence. The encryptor encrypts the first data-bit sequence as an encrypted-bit sequence. The framing-bit device substitutes on the encrypted-bit sequence, a second framing-bit sequence, thereby generating a framed- encrypted-bit sequence. The decryptor decrypts the framed-encrypted-bit sequence as a second data-bit sequence. The second data-bit sequence contains errors due to the second framing-bit sequence. A second framing-bit repositioner detects in the second data-bit sequence, the first framing-bit sequence and the errors. In response to detecting the errors and the first framing-bit sequence, the first framing-bit repositioner aligns the first framing-bit sequence with the second framing-bit sequence.

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